module lvds_top
  (
    input   					inclk,
    input						pll_rst,

    output	[1:0]			tx_rdy,

    input						cpu_nce,  //chip select enable ----cs
    input						cpu_noe,
    input						cpu_nwe,
    input		[15:0]		cpu_addr,
    inout		[15:0]		cpu_data,

    output    				tx,
    input						rx,
    output					clk_10M ,
    output               pll_locked
  );

  wire 				clk_100M,clk_400M;
  wire   			rst=!pll_locked;

  wire				tx_en;
  wire				rx_en;

  wire				tx_nce;
  wire				tx_noe;
  wire				tx_nwe;
  wire	[9:0]		tx_rd_addr_ab;
  wire	[15:0]	tx_data;
  wire	[15:0]	tx_rd_data;

  wire				rx_nce;
  wire				rx_noe;
  wire				rx_nwe;
  wire	[9:0]		rx_addr;
  wire	[15:0]	rx_data;
  wire	[15:0] 	rx_we_data;

  assign			tx_en		=(cpu_addr[15:10]==6'd0);
  assign			rx_en		=(cpu_addr[15:10]==6'd1);

  assign    		tx_nce	=tx_en?cpu_nce:1'b1;
  assign			rx_nce	=rx_en?cpu_nce:1'b1;

  assign         tx_nwe	=(~tx_nce)?cpu_nwe:1'b1;
  assign			rx_nwe	=(~rx_nce)?cpu_nwe:1'b1;

  assign			tx_noe	=(~tx_nce)?cpu_noe:1'b1;
  assign         rx_noe	=(~rx_nce)?cpu_noe:1'b1;

  assign			tx_rd_addr_ab=tx_en?cpu_addr[9:0]:10'd0;
  assign			rx_addr		 =rx_en?cpu_addr[9:0]:10'd0;


  assign			tx_data	    =tx_en?cpu_data:16'h0000;
  assign			rx_we_data	 =rx_en?cpu_data:16'h0000;

  assign			cpu_data		=(~tx_noe)?tx_rd_data:
           ((~rx_noe)?rx_data:16'hZZZZ);


  trans_data_buf   trans_data_buf_inst  //transmit data
                   (
                     .rst				(rst),
                     .clk_10M			(clk_10M),
                     .clk_100M		(clk_100M),
                     .tx_nce			(tx_nce),
                     .tx_noe			(tx_noe),
                     .tx_nwe			(tx_nwe),

                     .tx_rdy			(tx_rdy),
                     .tx_addr			(tx_rd_addr_ab),
                     .tx_data			(tx_data),
                     .tx_rd_data		(tx_rd_data),
                     .tx_out			(tx)
                   );

  recv_data_buf
    #(
      .SYNC1(10'b1010_1010_10),
      .SYNC2(10'b1010_1010_11)
    )
    recv_data_buf_inst
    (
      .rst						(rst),
      .clk_100M				(clk_100M),
      .clk_400M				(clk_400M),
      .rx						(rx),
      .rx_nce					(rx_nce),
      .rx_noe					(rx_noe),
      .rx_nwe					(rx_nwe),
      .rx_rdy					(rx_rdy),
      .rx_addr					(rx_addr),
      .rx_data					(rx_data),
      .rx_we_data				(rx_we_data)
    );

  plltx_rx	plltx_rx_inst (
             .areset (pll_rst ),
             .inclk0 ( inclk),
             .c0 ( clk_10M ),
             .c1 ( clk_100M),
             .c2 ( clk_400M ),
             .locked ( pll_locked )
           );

endmodule
